Hardware implementation of intelligent systems

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Novel energy-efficient leakage current minimization techniques for CMOS VLSI circuits

Leakage power loss is a major concern in deep-submicron technologies. High-performance processors and servers consume enormous amounts of operating power. For portable devices that have burst-mode type integrated circuits, it is acceptable to have leakage during the active mode. However, during the idle state it is extremely wasteful to have leakage, as power is unnecessarily consumed with no useful work being done. Efficient leakage control mechanisms are crucial for saving power. In this research, we propose novel leakage current minimization techniques for CMOS VLSI circuits. A combination of high-threshold and standard-threshold sleep transistors embedded within the CMOS topology was used in voltage balancing of the Pull-Up Network (PUN) as well as the Pull-Down Network (PDN), thereby shutting them off and minimizing leakage loss. An ultra-low power standard cell library which uses this technique that achieves cancellation of leakage effects in both the PUN and PDN for CMOS circuits, has been characterized for area, delay and power. A signal probability based self-controller was designed for leakage power reduction. It is the core of this work that sequences the working of these sleep-embedded cells in any VLSI circuit. Since signal probabilities are used to determine the mode of operation of these cells, there is no need for any extra external circuitry for this purpose. The ultra-low power standard library consists of 8 combinational and 2 sequential cells. Experimental results show significant leakage savings (an average of 20.7X) in CMOS circuits employing this sleep-circuitry when compared to standard CMOS circuits. A methodology to integrate the ultra low-power library and the self-controller into the low-power synthesis framework is also presented as part of this research. Comparison of our technique with other well-established leakage reduction techniques shows significant leakage savings of the former over the latter, with comparable area and delay performance degradation. Large leakage savings were observed even at higher temperatures. An analysis of these sleep-embedded circuits showed a negligible 0.42% increase in dynamic power dissipation. Our technique was also applied to the Differential Cascode Voltage Switch Logic (DCVSL) class of circuits. An order of leakage savings was observed, thereby demonstrating its effectiveness

A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures

This paper presents a novel technique to perform dynamic high-level exploration of a behavioral specification that is being partitioned for a multi-device architecture. The technique, unlike in traditional HLS, performs a global search on the four-dimensional design space formed by multiple partition segments of the behavior. Hence, the proposed technique effectively satisfies the global latency constraint on the entire design, as well as the area constraints on the individual partition segments. Since the technique is based on a rigorous exploration model, it employs an efficient lowcomplexity heuristic instead of an exhaustive search. We have provided a number of results by integrating the exploration technique with two popular partitioning algorithms: (i) simulated annealing and (ii) fiducciamattheyses. The proposed technique is highly effective in guiding any partitioning algorithm to a constraint satisfying solution, and in a fairly short execution time. At tight constraint values..